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w27c01 128k 8 electrically eras able eprom publication release date: april 15, 2002 - 1 - revision a 2 general description the w27c01 is a high speed, low power consumption electrically erasable and programmable read only memory organized as 131,072 x 8 bits. it requires only one supply in the range of 5.0v 5% in normal read mode. the w27c01 provides an electrical chip erase function. features single power supply voltage: 5.0v 5% high speed access time: 70 ns (max.) read operating current: 30 ma (max.) erase/programming operating current: 30 ma (max.) standby current: 20 m a (max.) +12v e rase/programming voltage fully static operation all inputs and outputs directly ttl/cmos compatible three - state outputs available packages: 32 - pin 600 mil dip, 32 - lead plcc and 32 - lead stsop pin configurations a6 a5 a4 a3 a2 a1 a0 q0 5 6 7 8 9 10 11 12 13 q 1 q 2 q 4 q 5 q 6 1 4 4 3 2 1 3 2 3 1 3 0 a14 a13 a8 a9 #oe a11 q7 29 28 27 26 25 24 23 22 21 32-lead plcc v s s 1 5 1 6 1 7 1 8 1 9 2 0 n c v d d #ce a10 a 1 5 a 1 6 q 3 a7 a 1 2 v p p # p g m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a3 a2 a1 a0 q0 q1 q2 #oe a10 #ce q7 q6 q5 q4 q3 32-lead stsop a15 a12 a7 a6 a5 a4 #pgm a14 a13 a8 v dd a11 a9 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a16 nc v ss v pp 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 q0 a0 a2 a3 a4 a5 a6 a7 a12 a15 a16 a1 vpp vss q2 q1 30 31 32 25 26 27 28 29 20 21 22 23 24 19 18 17 q5 #oe a10 q7 q6 a13 a8 a9 a11 #pgm nc a14 q3 q4 #ce v dd 32-pin pdip b lock diagram v vss dd v pp control output buffer decoder core array q0 q7 . . #ce #oe a0 . . a16 #pgm pin description symbol description a0 - a16 address inputs q0 - q7 data inputs/outputs #ce chip enable #oe output enable #pgm program enable v pp program/erase supply voltage v dd power supply v ss ground nc no connection
w27c01 - 2 - functional descripti on read mode like conventional uveproms, the w27c01 has two control functions and both of these produce data at the outputs. #ce is for power control and chip select. #oe controls the output buffer to gate data to the output pins. when addresses are stable, the address access time (t acc ) is equal to the delay from #ce to output (t ce ), and data are available at the outputs t oe after the falling edge of #oe, if t acc and t ce timings are met. erase mode the erase operat ion is the only way to change data from "0" to "1." unlike conventional uveproms, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the w27c01 uses electrical erasure. generally, the chip c an be erased within 100 ms by using an eprom writer with a special erase algorithm. erase mode is entered when v pp is raised to v pe (12v), v dd = v ce (5v), #ce low, #oe high, a9 = v hh (12v), a0 low , and all other address pins low and data input pins high. p ulsing #pgm low starts the erase operation. erase verify mode after an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. the erase verify mode automatically ensures a substanti al erase margin. this mode will be entered after the erase operation if v dd = v pe (5v), #ce low, and #oe low, #pgm high . program mode programming is performed exactly as it is in conventional uveproms, and programming is the only way to change cell data f rom "1" to "0." the program mode is entered when v pp is raised to v pp (12v), v dd = v cp (5v), #ce low, #oe high, the address pins equal the desired addresses, and the input pins equal the desired inputs. pulsing #pgm low starts the programming operation. pr ogram verify mode all of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. hence, after each byte is programmed, a program verify operation should be performed. the program verify m ode automatically ensures a substantial program margin. this mode will be entered after the program operation if v pp = v pp (12v), #ce low, #oe low , and #pgm high. erase/program inhibit erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. when #ce high , erasing or programming of non - target chips is inhibited, so that except for the #ce, the w27c01 may have common inputs. standby mode the standby mode significantly reduces v dd current. this mode is ente red when #ce high. in standby mode, all outputs are in a high impedance state, independent of #oe and #pgm.
w 27c01 publication release date: april 15, 2002 - 3 - revision a 2 two - line output control since eproms are often used in large memory arrays, the w27c01 provides two control inputs for multiple memory connections. two - line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur. system considerations eprom power switching characteristics require careful device decoupling. system designers are concerned with t hree supply current issues: standby current levels (i sb ), active current levels (i cc ), and transient current peaks produced by the falling and rising edges of #ce. transient current magnitudes depend on the device output's capacitive and inductive loading. two - line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1 m f ceramic capacitor connected between its v dd and vss. this high frequency, low inherent - inductance capacitor should be placed as close as possible to the device. additionally, for every eight devices, a 4.7 m f electrolytic capacitor should be placed at the array's power supply connection between v dd and vss. the bulk capacitor will overcome voltage slumps caused by pc board trac e inductances. table of operating m odes v dd = 5.0v 5 %, vpp = vp e = v hh = 12v, v cp = v pe = 5v, x = v ih or v il mode pins #ce #oe #pgm a0 a9 v dd v pp outputs read v il v il x x x v dd v dd d out output disable v il v ih x x x v dd v dd high z standby (ttl) v ih x x x x v dd v dd high z standby (cmos) v dd 0.3v x x x x v dd v dd high z program v il v ih v il x x v cp v pp d in program verify v il v il v ih x x v cp v pp d out program inhibit v ih x x x x v cp v pp high z erase v il v ih v il v il v pe v cp v pe ff (hex) erase ver ify v il v il v ih x x v pe v pe d out erase inhibit v ih x x x x v cp v pe high z product identifier - m anufacturer v il v il x v il v hh v dd v dd da (hex) product identifier - d evice v il v il x v ih v hh v dd v dd 01 (hex)
w27c01 - 4 - dc characteristics absolute maximum ratings par ameter rating unit operation temperature 0 to +70 c storage temperature - 65 to +125 c voltage on all pins with respect to ground except v dd, v pp and a9 pins - 0.5 to v dd +0.5 v voltage on v dd pin with respect to ground - 0.5 to +7.0 v voltage on v pp p in with respect to ground - 0.5 to +14.5 v voltage on a9 pin with respect to ground - 0.5 to +14.5 v note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. capacitance (v dd = 5.0v 5 %, t a = 25 c, f = 1 mhz) parameter symbol conditions max. unit input capacitance c in v in = 0v 6 pf output capacitance c out v out = 0v 12 pf read operation dc ch aracteristics (v dd = 5.0v 5%, t a = 0 to 70 c) parameter sym. conditions lim its unit min. typ. max. input load current i li v in = 0v to v dd - 5 - 5 m a output leakage current i lo v out = 0v to v dd - 10 - 10 m a standby v dd current (ttl input) i sb #ce = v ih - - 1 ma standby v dd current (cmos input) i sb 1 #ce = v dd 0.2v - - 1 00 m a v dd operating current i cc #ce=v il, i out = 0 ma, f = 5 mhz - - 30 ma v pp operating current i pp v pp = v dd - - 10 m a input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.2 - v dd +0.5 v output low voltage v ol i ol = 1.6 ma - - 0.4 v outpu t high voltage v oh i oh = - 0.1 ma 2.4 - - v v pp operating voltage v pp - v dd - 0.7 - v dd v
w 27c01 publication release date: april 15, 2002 - 5 - revision a 2 program/erase dc characteristics (t a = 25 c, v dd = 5.0v 5 %, v hh = 12v) parameter sym. conditions limits unit min. typ. max. input load current i li v in = v il or v ih - 10 - 10 m a v dd program current i cp #ce = v il, #oe = v ih, #pgm = v il - - 30 ma v dd erase current i ce #ce = v il, #oe = v ih, #pgm = v il , a9 = v hh - - 30 ma v pp program current i pp #ce = v il, #oe = v ih, #pgm = v il - - 30 ma v pp erase current i p e #ce = v il, #oe = v ih, #pgm = v il , a9 = v hh - - 30 ma input low voltage v il - - 0.3 - 0.8 v input high voltage v ih - 2.4 - 5.5 v output low voltage (verify) v ol i ol = 2.1 ma - - 0.45 v output high voltage (verify) v oh i oh = - 0.4 ma 2.4 - - v a9 silico n i.d. voltage v id - 11.5 12.0 12.5 v a9 erase voltage v id - 11.75 12.0 14.25 v v pp program voltage v pp - 11.75 12.0 12.25 v v pp erase voltage v pe - 11.75 12.0 14.25 v v dd supply voltage (program) v cp - 4.5 5.0 5.5 v v dd supply voltage (erase) v ce - 4 .5 5.0 5.5 v v dd supply voltage (erase verify) v pe - - 5.0 - v note: v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp .
w27c01 - 6 - ac characteristics ac test conditions parameter conditions input pulse levels 0v to 3.0v in put rise and fall times 5 ns input and output timing reference level 1.5v/1.5v output load c l = 100 pf, i oh /i ol = - 0.1 ma/1.6 ma for read i oh /i ol = - 0.4 ma/2.1 ma for program/erase ac test load and waveforms +1.3v 3.3k ohm 100 pf (including jig and scope) d (in914) out 3.0v 0v 1.5v test points test points input output 1.5v
w 27c01 publication release date: april 15, 2002 - 7 - revision a 2 read opera tion ac characterist ics (v dd = 5.0v 5 %, t a = 0 to 70 c) parameter symbol w27c01 - 70 unit min. max. read cycle time t rc 70 - ns chip enable access time t ce - 70 ns address access time t acc - 70 ns output enable access time t oe - 30 ns #oe high t o high - z output t df - 25 ns output hold from address change t oh 0 - ns note: v dd must be applied simultaneously or before v pp and removed simultaneously or after v pp . ac programming/erase characteristics (v dd = 5.0v 5%, t a = 25 c ) parameter symbol lim its unit min. typ. max. v pp setup time t vps 2.0 - - m s address setup time t as 2.0 - - m s data setup time t ds 2.0 - - m s #pgm program pulse width t pwp 95 100 105 m s #pgm erase pulse width t pwe 95 100 105 ms data hold time t dh 2.0 - - m s #oe se tup time t oes 2.0 - - m s data valid from #oe t oev - - 150 ns #oe high to output high z t dfp 0 - 130 ns address hold time after #pgm high t ah 0 - - m s address hold time (erase) t ahe 2.0 - - m s #ce setup time t ces 2.0 - - m s note: v dd must be applied s imultaneously or before v pp and removed simultaneously or after v pp .
w27c01 - 8 - timing waveforms ac read waveform #ce outputs t high z high z valid output ce t oe t acc t oh t df address address valid v il v ih v ih v il v ih v il #oe erase waveform address read sid device read sid a9 = 12.0v others = v il a0 = v il data chip erase a9 = 12.0v erase verify address stable t as da data all one 12.0v 5v a0=v ih read verify blank check manufacturer address stable address stable others=v il others = v il t as t as t ahc t ds t dh t vps t dfp d out d out d out t ah t acc v ih v il v pp #ce #oe #pgm t ce t oe t oe t oes t oev t pwe t ces t oe v ih v il v ih v il = vdd
w 27c01 publication release date: april 15, 2002 - 9 - revision a 2 timing waveforms, continued programming waveform address data 12.0v 5.0v #ce address stable program read verify address stable address valid verify data in stable 5v program d out t ah d out d out t dh t ds t vps t ces t acc t dfp t as v ih v il v ih v il v pp #oe t oes t oev t oe v ih v il #pgm t pwp v ih v il
w27c01 - 10 - smart programming al gorithm start address = first location vdd = 5v vpp = 12v x = 0 increment x x = 25? verify one byte last address? vdd = 5v vpp = 5v compare all bytes to original data pass device increment address no fail yes pass fail fail fail device verify one byte program one 100 s pulse m no pass yes pass
w 27c01 publication release date: april 15, 2002 - 11 - revision a 2 smart erase algorith m start vdd = 5v vpp = 12v x = 0 a9 = 12v; a0 = v chip erase 100 ms pulse address = first location il compare all bytes to ffs (hex) pass device fail device pass vdd = 4.5v vpp = 4.5v fail x = 20? yes no increment x
w27c01 - 12 - ordering information part no. access time ( n s) power supply current max. ( m a) standby v dd current max. ( m a) package w27c01 - 70 70 30 20 600 mi l dip w27c01p - 70 70 30 20 32 - lead plcc w27c01q - 70 70 30 20 32 - lead stsop notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on pro ducts intended for use in applications where personal injury might occur as a consequence of product failure.
w 27c01 publication release date: april 15, 2002 - 13 - revision a 2 package dimensions 32 - pin p - dip seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. notes: 4. dimension b1 does not include dambar protrusion/intrusion. 5. controlling dimension: inches. 1.37 1.22 0.054 0.048 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.540 0.555 0.550 13.84 14.10 13.97 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 0 15 0.085 2.16 0.650 0.630 16.00 16.51 15 0 32 - lead plcc l c 1 b 2 a h e e e b d h d y a a 1 seating plane e g g d 1 13 14 20 29 32 4 5 21 30 notes: 1. dimensions d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: inches. 4. general appearance spec. should be based on final visual inspection sepc. q symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 g d 3.56 0.50 h d g e 0.020 0.140 2.80 2.67 2.93 0.71 0.66 0.81 0.41 0.46 0.56 0.20 0.25 0.35 13.89 13.97 14.05 11.35 11.43 11.51 1.27 12.45 12.95 13.46 0.530 0.510 0.490 0.050 0.453 0.450 0.447 0.553 0.550 0.547 0.014 0.010 0.008 0.022 0.018 0.016 0.032 0.026 0.028 0.115 0.105 0.110 1.12 1.42 0.044 0.056 0 10 10 0 9.91 10.41 10.92 14.86 14.99 15.11 12.32 12.45 12.57 1.91 2.29 0.004 0.095 0.090 0.075 0.495 0.490 0.485 0.595 0.590 0.585 0.430 0.410 0.390 0.10 2.41 q
w27c01 - 14 - package dimensions, continued 32 - lead stsop (8 x 14 mm) min. dimension in inches nom. max. min. nom. max. symbol 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.10 0.50 0.00 0 0.22 0.27 ----- 0.21 12.40 8.00 14.00 0.50 0.60 0.70 0.80 0.10 3 5 0.047 0.006 0.041 0.040 0.035 0.007 0.009 0.010 0.004 ----- 0.008 0.488 0.315 0.551 0.020 0.020 0.024 0.028 0.031 0.000 0.004 0 3 5 0.002 a a b c d e e l l y 1 1 2 a h d q dimension in mm a a a 2 1 l l 1 y c e h d d c b e
w 27c01 publication release date: april 15, 2002 - 15 - revision a 2 version history version date page description a1 apr. 2001 - initial issued a2 april 15, 2002 all modify by w27e01 except v dd = 5.0v 5% 5 modify by w27e01 except v ih = 2.2v (min.) for read operation. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu chiu, taipei, 114, taiwan, r.o.c.

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